1. Field of the Invention
The present invention relates generally to multi-chip package products and, more particularly, to a multi-memory chip containing two or more memory devices and a method of transferring data between the internal devices of the multi-memory chip.
2. Description of the Related Art
With ever-increasing demand in the semiconductor industry, the trend is toward smaller and more lightweight electronic devices. Accordingly, Multi-Chip Packaging (MCP) technology, in which a plurality of devices are constructed in a common package have become popular. An example of the application of MCP technology is a multi-memory chip, in which a flash memory device and a Static Random Access Memory (SRAM) device are constructed as a single Thin Small Outline Package (TSOP).
In the meantime, each of the memory devices included in the multi-memory chip can independently transfer data with an external system. That is, each memory device can read stored data and output the read data to the external system, and can receive data from the external system and write the received data to memory. In addition, in certain cases, data can be read from one of the memory devices included in the multi-memory chip and written to one or more of the other memory devices.
With reference to FIGS. 1 and 2, the transfer of data between two memory devices 110 and 160 included in a conventional multi-memory chip is performed using a Direct Memory Access (DMA) 220 controller included in an external system 200. That is, during interval T11 of FIG. 3, flash memory 110 is controlled to operate in a read mode and read data are provided to the memory interface 210 of the external system 200. At this time, the flash memory 110 activates a waiting indication signal WAITB providing advance notice of the output of the data, and provides the signal WAITB to the memory interface 210.
During interval T12 of FIG. 3, the data read from the flash memory 110 are stored in the DMA 220. Thereafter, in interval T13 of FIG. 3, when an SRAM 160 is controlled to operate in a write mode, the data read from the flash memory 110 and stored in the DMA 220 are provided to the SRAM 160. At this time, the SRAM 160 activates the waiting indication signal WAITB requesting the transmission of data, and provides the signal WAITB to the memory interface 210.
Meanwhile, in accordance with the conventional multi-memory chip and the method of transferring data between the internal devices of the multi-memory chip illustrated in FIGS. 1 to 3, the transfer of data between the memory devices is also performed through the DMA controller of the external system by transporting the data through the external DMA controller. Accordingly, there is a problem in that the time required for the transfer of data between memory devices can be excessively long.